1. Field of the Invention
The present invention generally relates to magnetic random access memory (MRAM). More particularly, this invention relates to maximizing the total yield of MRAM, by making MRAM which has the ability to adapt the row and column programming currents for individual cells which allows MRAM to be used as either static RAMs, one-time-programmable RAMs or electrically alterable or flash RAMs.
2. Description of the Prior Art
A typical MRAM memory cell with an isolation transistor is shown in FIG. 1. A bit line 110 and its current 120 and the resultant magnetic field 130 are shown in FIG. 1. In addition, a word line 140 and its current 170 and the resultant magnetic field 160 are shown in FIG. 1. The three layers that comprise the memory cell are shown in FIG. 1. Two layers of ferromagnetic material, the free layer 180 and the pinned layer 195 are shown above and below an insulation layer such as oxide 190. An isolation transistor is also shown in FIG. 1. The MTJ, Magnetic Tunnel Junction, exhibits a hysteresis characteristic as shown in FIG. 2. Two distinct states of a memory cell are based on its resistance ratio whether the free layer and pinned layer magnetic fields are parallel or anti-parallel. The ratio of increase in resistance (delta R) when the fields are anti-parallel can be up to 50% with present technology. In order to write two different states into cells, cross points of two current components are needed. In FIG. 2, the word line current is equivalent to the row current (IR) and the bit line current is equivalent to the column current (IC). FIG. 2 shows two hysteresis loops of a single MTJ. When word line current is 0 mA, it requires +−7.5 mA of bit line current to switch the field direction of free layer. However, when there is 4 mA word line current, the bit line current needed to switch the field direction of the free layer is around +−2.5 mA. The resistance of MTJ changed from 7.6 kohm to 10.5 kohm, a 38% increase. FIG. 2 also shows a slight asymmetry in the hysteresis in that more bit line current is required to switch the MTJ from low resistance to high resistance than the other way around. In FIG. 3, the minimum word line and bit line currents needed to switch the magnetic field of the free layer of a single MTJ are shown. Any bias point (combination of word line/row current, IR and bit line/column current, IC) inside the asteroid area 310 will not switch the direction of free layer magnetic field. Any points outside the asteroid 310 area will switch the direction of magnetic field or unintentionally disturb the MTJs sharing the same word line or bit line. When a large number of MTJs used to make a memory array, the characteristics of each MTJ may vary significantly due to random process variation. The asteroid chart of FIG. 3 will be the composite of all the MTJs in the array. Choosing a fixed biasing point (IR and IC) such that all the MTJs can be switched in both directions and not disturbing MTJs along the same row or column can be a difficult task.
The MRAM cells forming a memory array are organized in rows and columns. They are programmed by row current and column current. The cells at cross points of the row and column programming currents get programmed. The cells sharing the same row and column lines will see its respective row or column current. These cells must not be unintentionally programmed or disturbed with one of the current components. Due to the randomness of the manufacturing process, the current levels needed to program the intended cells and not to disturb the cells sharing the same row line and bit Line will be different for the entire memory array. The problem gets significantly worse when the array is very big.
By partitioning the array into local word lines, as in FIG. 4, the possible disturbs will only occur on the cells sharing same bit lines of the byte being programmed. By adjusting the programming currents for each byte, the probability of programming every cell and not disturbing other cells in a memory array is greatly improved. FIG. 4 shows segment N−1 (470) and segment N (480) where N is any number from 1 increasing. Segment N−1 memory cells 410 are shown along with a segmented word line select transistor 491. The segmented word line select transistor 491 has a return line attached to the Global Word line return 450. The segmented word line select transistors along with the global word line 420 are used to include or exclude a segment, byte or group of bytes from the effects of memory cell programming. The global word lines such as 420 in FIG. 4 and the local word lines such as 490 in FIG. 4 are the rows referred to in FIG. 1 and the bit lines 460 in FIG. 4 are the columns referred to in FIG. 1.
FIG. 6 shows a non volatile latch implemented with MTJ and FIG. 5 shows an adaptive current source which can be programmed by the non volatile latches to adjust the current level. They are shown as one way of changing programming current. Any one well versed in this art can implement adaptive current sources in many different ways. FIG. 5 uses the latch cells 510 detailed in FIG. 6. There are three current sources 520 which are selectively combined using the selective activation of transistor devices such as 530. A combined, total current, (I total), 550, is the resultant adaptive current. A Vdd power supply 540 is shown supplying the power to the current sources, I1, I2, and I3.
In FIG. 6, non-volatile latch is implemented with two p-channel metal oxide semiconductor field effect transistors, PMOS FETs, 610, 630, two n-channel metal oxide semiconductor field effect transistors, NPMOS FETs, 620, 640, two variable resistors, preferably MJTs, 670, 680 and two inverters, 650, 655. A Vdd power supply, 690, and ground 695 are shown. In addition, the latch outputs are 655 and 665, and the latch inputs are 675 and 685.
As stated above, due to the randomness of the manufacturing process, the current levels needed to program the intended cells and not to disturb the cells sharing the same row line and bit Line will be different for the entire memory array. Today's technology allows the building of larger and larger MRAM arrays causing the above problems to get even worse. Even with the segmenting of arrays described above, many magnetic chips must be discarded, since a viable combination of row current and column current cannot be found which fits into the asteroid area 310 of FIG. 3.                U.S. Pat. No. 6,639,848 (Maejima) discloses die testing of MRAM or EEPROM devices to detect defective chips and recover them if possible.        U.S. Pat. No. 6,639,859 (Tran) shows a test apparatus to test arrays of various sizes.        U.S. Pat. No. 6,477,081 (Poechmueller) describes a method for testing MRAM memory cells.        